Freescale Semiconductor MPC5604B - DSPI Module Configuration Register (Dspix_Mcr)

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 475
23.5.2 DSPI Module Configuration Register (DSPIx_MCR)
The DSPIx_MCR contains bits which configure attributes of the DSPI operation. The values of the HALT
and MDIS bits can be changed at any time, but their effect begins on the next frame boundary. The HALT
and MDIS bits in the DSPIx_MCR are the only bit values software can change while the DSPI is running.
Offset: 0x00 Access: Read/write
0123456789101112131415
R
MSTR
CONT_SCKE
DCONF FRZ
MTFE
PCSSE
ROOE
00
PCSIS5 PCSIS4 PCSIS3 PCSIS2 PCSIS1 PCSIS0
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
MDIS
DIS_TXF
DIS_RXF
CLR_TXF
CLR_RXF
SMPL_PT
0000000
HALT
W
Reset0100000000000001
Figure 23-3. DSPI Module Configuration Register (DSPIx_MCR)
Table 23-3. DSPIx_MCR field descriptions
Field Description
MSTR Master/slave mode select
Configures the DSPI for master mode or slave mode.
0 DSPI is in slave mode
1 DSPI is in master mode
CONT_SCKE Continuous SCK enable
Enables the serial communication clock (SCK) to run continuously. See Section 23.6.6,
Continuous serial communications clock, for details.
0 Continuous SCK disabled
1 Continuous SCK enabled
Note: If the FIFO is enabled with continuous SCK mode, the TX-FIFO should be cleared before
setting the CONT_SCKE bit, and only the CTAR0 register should be used to transfer
attributes; otherwise, a change in SCK frequency occurs.