MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 717
• Single AHB port interface supports a 32-bit data bus. All AHB aligned and unaligned reads within
the 32-bit container are supported. Only aligned word writes are supported.
• Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank
• Interface with code flash memory (bank0) provides configurable read buffering and page prefetch
support. Four page read buffers (each 128 bits wide) and a prefetch controller are used to support
single-cycle read responses (zero AHB data phase wait-states) for hits in the buffers. The buffers
implement a least-recently-used replacement algorithm to maximize performance.
• Interface with optional data flash memory (bank1) includes a 128-bit register to temporarily hold
a single flash memory page. This logic supports single-cycle read responses (zero AHB data phase
wait-states) for accesses that hit in the holding register. There is no support for prefetching
associated with this bank.
• Programmable response for read-while-write sequences including support for stall-while-write,
optional stall notification interrupt, optional flash memory operation abort, and optional abort
notification interrupt
• Separate and independent configurable access timing (on a per bank basis) to support use across a
wide range of platforms and frequencies
• Support of address-based read access timing for emulation of other memory types
• Support for reporting of single- and multi-bit flash memory ECC events
• Typical operating configuration loaded into programming model by system reset
27.7.2 Memory map and register description
Two memory maps are associated with the platform flash memory controller: one for the flash memory
space and another for the program-visible control and configuration registers. The flash memory space is
accessed via the AMBA-AHB port and the program-visible registers are accessed via the slave peripheral
bus. Details on both memory spaces are provided in Section 27.7.2.1, Memory map.
There are no program-visible registers that physically reside inside the platform flash memory controller.
Rather, the platform flash memory controller receives control and configuration information from the flash
memory array controller(s) to determine the operating configuration. These are part of the flash memory
array’s configuration registers mapped into its slave peripheral (IPS) address space but are described here.
27.7.2.1 Memory map
First, consider the flash memory space accessed via transactions from the platform flash memory
controller’s AHB port.
To support the two separate flash memory banks, each up to 8 MB in size, the platform flash memory
controller uses address bit 23 (haddr[23]) to steer the access to the appropriate memory bank. In addition
to the actual flash memory regions, the system memory map includes shadow and test sectors. The
program-visible control and configuration registers associated with each memory array are included in the
slave peripheral address region. The system memory map defines one code flash memory array and one
data flash memory array. See Table 27-56.
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