MPC5604B/C Microcontroller Reference Manual, Rev. 8
110 Freescale Semiconductor
Figure 6-10. Frequency modulation
6.7.6.4 Powerdown mode
To reduce consumption, the FMPLL can be switched off when not required by programming the registers
ME_x_MC on the MC_ME module.
6.7.7 Recommendations
To avoid any unpredictable behavior of the FMPLL clock, it is recommended to follow these guidelines:
• The FMPLL VCO frequency should reside in the range 256 MHz to 512 MHz. Care is required
when programming the multiplication and division factors to respect this requirement.
• The user must change the multiplication, division factors only when the FMPLL output clock is
not selected as system clock. Use progressive clock switching if system clock changes are required
while the PLL is being used as the system clock source. MOD_PERIOD, INC_STEP,
SPREAD_SEL bits should be modified before activating the FM mode. Then strobe has to be
generated to enable the new settings. If STRB_BYP is set to ‘1’ then MOD_PERIOD, INC_STEP
and SPREAD_SEL can be modified only when FMPLL is in powerdown mode.
• Use progressive clock switching (FMPLL output clock can be changed when it is the system clock,
but only when using progressive clock switching).
6.8 Clock monitor unit (CMU)
6.8.1 Introduction
The Clock Monitor Unit (CMU), also referred to as Clock Quality Checker or Clock Fault Detector, serves
two purposes. The main task is to permanently supervise the integrity of the various clock sources, for
example a crystal oscillator or FMPLL. In case the FMPLL leaves an upper or lower frequency boundary
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