MPC5604B/C Microcontroller Reference Manual, Rev. 8
302 Freescale Semiconductor
17.3 Overview
The XBAR allows for concurrent transactions to occur from any master port to any slave port. It is possible
for all master ports and slave ports to be in use at the same time as a result of independent master requests.
If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher
priority master and grants it ownership of the slave port. All other masters requesting that slave port are
stalled until the higher priority master completes its transactions.
Requesting masters are granted access based on a fixed priority.
17.4 Features
• 2 master ports:
— Core: e200z0 core instructions
— Core: e200z0 core data / Nexus
• 3 slave ports
— Flash (refer to the flash memory chapter for information on accessing flash memory)
— Internal SRAM
— Peripheral bridges
• 32-bit address, 32-bit data paths
• Fully concurrent transfers between independent master and slave ports
• Fixed priority scheme and fixed parking strategy
17.5 Modes of operation
17.5.1 Normal mode
In normal mode, the XBAR provides the logic that controls crossbar switch configuration.
17.5.2 Debug mode
The XBAR operation in debug mode is identical to operation in normal mode.
17.6 Functional description
This section describes the functionality of the XBAR in more detail.
17.6.1 Overview
The main goal of the XBAR is to increase overall system performance by allowing multiple masters to
communicate concurrently with multiple slaves. To maximize data throughput, it is essential to keep
arbitration delays to a minimum.
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