Freescale Semiconductor MPC5604B - Functional Description

MPC5604B/C Microcontroller Reference Manual, Rev. 8
726 Freescale Semiconductor
27.8 Functional description
The platform flash memory controller interfaces between the AHB system bus and the flash memory
arrays.
The platform flash memory controller generates read and write enables, the flash memory array address,
write size, and write data as inputs to the flash memory array. The platform flash memory controller
captures read data from the flash memory array interface and drives it onto the AHB. Up to four pages of
data (128-bit width) from bank0 are buffered by the platform flash memory controller. Lines may be
prefetched in advance of being requested by the AHB interface, allowing single-cycle (zero AHB
wait-states) read data responses on buffer hits.
Several prefetch control algorithms are available for controlling page read buffer fills. Prefetch triggering
may be restricted to instruction accesses only, data accesses only, or may be unrestricted. Prefetch
triggering may also be controlled on a per-master basis.
Buffers may also be selectively enabled or disabled for allocation by instruction and data prefetch; see
Section 27.7.2.2.1, Platform Flash Configuration Register 0 (PFCR0), and Section 27.7.2.2.2, Platform
Flash Configuration Register 1 (PFCR1).
Access protections may be applied on a per-master basis for both reads and writes to support security and
privilege mechanisms; see Section 27.7.2.2.3, Platform Flash Access Protection Register (PFAPR).
Offset: 0x203E00 Access: Read/write
0123456789101112131415
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
M0PFD
W
Reset
1111111111111111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0
M0AP
W
Reset
1111111111111111
Figure 27-42. Nonvolatile Platform Flash Access Protection Register (NVPFAPR)
Table 27-61. NVPFAPR field descriptions
Field Description
M0PFD See Table 27-60.
M0AP See Table 27-60.