Freescale Semiconductor MPC5604B - TAP Controller State Machine

MPC5604B/C Microcontroller Reference Manual, Rev. 8
792 Freescale Semiconductor
Data is shifted between TDI and TDO though the selected register starting with the least significant bit, as
illustrated in Figure 32-4. This applies for the instruction register, test data registers, and the bypass
register.
Figure 32-4. Shifting data through a register
32.8.3 TAP controller state machine
The TAP controller is a synchronous state machine that interprets the sequence of logical values on the
TMS pin. Figure 32-5 shows the machine’s states. The value shown next to each state is the value of the
TMS signal sampled on the rising edge of the TCK signal.
As Figure 32-5 shows, holding TMS at logic 1 while clocking TCK through a sufficient number of rising
edges also causes the state machine to enter the test-logic-reset state.
Selected register
MSB
LSB
TDI
TDO