MPC5604B/C Microcontroller Reference Manual, Rev. 8
532 Freescale Semiconductor
24.3.4 Functional description
The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and
application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare
channels with a separate interrupt source for each channel.
The STM has one 32-bit up counter (STM_CNT) that is used as the time base for all channels. When
enabled, the counter increments at the system clock frequency divided by a prescale value. The
STM_CR[CPS] field sets the divider to any value in the range from 1 to 256. The counter is enabled with
the STM_CR[TEN] bit. When enabled in normal mode the counter continuously increments. When
enabled in debug mode the counter operation is controlled by the STM_CR[FRZ] bit. When the
STM_CR[FRZ] bit is set, the counter is stopped in debug mode, otherwise it continues to run in debug
mode. The counter rolls over at 0xFFFF_FFFF to 0x0000_0000 with no restrictions at this boundary.
The STM has four identical compare channels. Each channel includes a channel control register
(STM_CCRn), a channel interrupt register (STM_CIRn) and a channel compare register (STM_CMPn).
The channel is enabled by setting the STM_CCRn[CEN] bit. When enabled, the channel will set the
STM_CIR[CIF] bit and generate an interrupt request when the channel compare register matches the timer
counter. The interrupt request is cleared by writing a 1 to the STM_CIRn[CIF] bit. A write of 0 to the
STM_CIRn[CIF] bit has no effect.
NOTE
STM counter does not advance when the system clock is stopped.
24.4 Enhanced Modular IO Subsystem (eMIOS)
24.4.1 Introduction
24.4.1.1 Overview of the eMIOS module
The eMIOS provides functionality to generate or measure time events. The eMIOS uses timer channels
that are reduced versions of the unified channel (UC) module used on MPC555x devices. Each channel
provides a subset of the functionality available in the unified channel, at a resolution of 16 bits, and
provides a user interface that is consistent with previous eMIOS implementations.
24.4.1.2 Features of the eMIOS module
• 2 eMIOS blocks with 28 channels each
— 50 channels with OPWMT, which can be connected to the CTU
— 6 channels with single action IC/OC
Table 24-8. STM_CMPn field descriptions
Field Description
CMP Compare value for channel n. If the STM_CCRn[CEN] bit is set and the STM_CMPn register matches the
STM_CNT register, a channel interrupt request is generated and the STM_CIRn[CIF] bit is set.
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