MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 107
6.7.6 Functional description
6.7.6.1 Normal mode
In Normal Mode the FMPLL inputs are driven by the CR. This means that, when the FMPLL is in lock
state, the FMPLL output clock (PHI) is derived by the reference clock (XOSC) through this relation:
where the value of IDF, NDIV and ODF are set in the CR and can be derived from Table 6-10, Table 6-11
and Table 6-12.
Table 6-13. MR field descriptions
Field Description
STRB_BYPASS Strobe bypass.
The STRB_BYPASS signal is used to bypass the strobe signal used inside FMPLL to latch the
correct values for control bits (INC_STEP, MOD_PERIOD and SPRD_SEL).
0 Strobe is used to latch FMPLL modulation control bits
1 Strobe is bypassed. In this case control bits need to be static. The control bits must be changed
only when FMPLL is in powerdown mode.
SPRD_SEL Spread type selection.
The SPRD_SEL controls the spread type in Frequency Modulation mode.
0 Center SPREAD
1 Down SPREAD
MOD_PERIOD Modulation period.
The MOD_PERIOD field is the binary equivalent of the value modperiod derived from following
formula:
where:
f
ref
: represents the frequency of the feedback divider
f
mod
: represents the modulation frequency
FM_EN Frequency Modulation Enable. The FM_EN enables the frequency modulation.
0 Frequency modulation disabled
1 Frequency modulation enabled
INC_STEP Increment step.
The INC_STEP field is the binary equivalent of the value incstep derived from following formula:
where:
md: represents the peak modulation depth in percentage (Center spread -- pk-pk=+/-md,
Downspread -- pk-pk=-2×md)
MDF: represents the nominal value of loop divider (CR[NDIV])
modperiod
f
ref
4f
mod
--------------------
=
incstep round
2
15
1–md MDF
100 5 MODPERIOD
---------------------------------------------------------------
=
phi
clkin NDIV
IDF ODF
----------------------------------
=
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