MPC5604B/C Microcontroller Reference Manual, Rev. 8
96 Freescale Semiconductor
reaches the value EOCV[7:0]×512, the oscillator clock is made available to the system. Also, an interrupt
pending FXOSC_CTL[I_OSC] bit is set. An interrupt is generated if the interrupt mask bit M_OSC is set.
The oscillator circuit can be bypassed by setting FXOSC_CTL[OSCBYP]. This bit can only be set by
software. A system reset is needed to reset this bit. In this bypass mode, the output clock has the same
polarity as the external clock applied on the EXTAL pin and the oscillator status is forced to ‘1’. The
bypass configuration is independent of the powerdown mode of the oscillator.
Table 6-2 shows the truth table of different oscillator configurations.
The FXOSC clock can be further divided by a configurable factor in the range 1 to 32 to generate the
divided clock to match system requirements. This division factor is specified by FXOSC_CTL[OSCDIV]
field.
6.3.3 Register description
Table 6-2. Truth table of crystal oscillator
ME_xxx_MC[FXOSCON]
FXOSC_CTL[OSCBYP
]
XTAL EXTAL FXOSC Oscillator mode
0 0 No crystal,
High Z
No crystal,
High Z
0 Powerdown, IDDQ
x 1 x Ext clock EXTAL Bypass, OSC
disabled
1 0 Crystal Crystal EXTAL Normal, OSC
enabled
Gnd Ext clock EXTAL Normal, OSC
enabled
Address: 0xC3FE_0000 Access: Special read/write
0123456789101112131415
R
OSCBYP
1
1
You can read this field, and you can write a value of “1” to it. Writing a “0” has no effect. A reset will also clear this bit.
0000000
EOCV
W
RESET:
0000000010000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
M_OSC
00
OSCDIV
I_OSC
2
0000000
W
RESET:
0000000000000000
Figure 6-2. Fast External Crystal Oscillator Control Register (FXOSC_CTL)
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