MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 731
0 AHB wait-states as the stored read data is routed from the temporary register back to the requesting bus
master.
The contents of the holding register are invalidated by the flash memory array at the beginning of all
program/erase operations and on any non-sequential access with a non-zero value on haddr[28:24] (to
support wait-state emulation) in the same manner as the bank0 page buffers. Additionally, the B1_P0_BFE
register bit can be cleared by software to invalidate the contents of the holding register.
As noted in Section 27.8.7, Flash error response operation, the temporary holding register is not marked
as valid if the flash memory array access terminated with any type of transfer error. However, the result is
that flash memory array accesses that are tagged with a single-bit correctable ECC event are loaded into
the temporary holding register and validated. Accordingly, one special case needing software invalidation
relates to holding register “hits” on flash memory data which was tagged with a single-bit ECC event.
Depending on the specific hardware configuration, the reporting of a single-bit ECC event may generate
an ECC alert interrupt. In order to prevent repeated ECC alert interrupts, the page buffers need to be
invalidated by software after the first notification of the single-bit ECC event.
The bank1 temporary holding register effectively operates like a single page buffer.
27.8.10 Read-while-write functionality
The platform flash memory controller supports various programmable responses for read accesses while
the flash memory is busy performing a write (program) or erase operation. For all situations, the platform
flash memory controller uses the state of the flash memory array’s MCR[DONE] output to determine if it
is busy performing some type of high voltage operation, namely, if MCR[DONE] = 0, the array is busy.
Specifically, two 3-bit read-while-write (BKn_RWWC) control register fields define the platform flash
memory controller’s response to these types of access sequences. Five unique responses are defined by the
BKn_RWWC setting: one that immediately reports an error on an attempted read and four settings that
support various stall-while-write capabilities. Consider the details of these settings.
• BKn_RWWC = 0b0--
For this mode, any attempted flash memory read to a busy array is immediately terminated with an
AHB error response and the read is blocked in the controller and not seen by the flash memory
array.
• BKn_RWWC = 0b111
This defines the basic stall-while-write capability and represents the default reset setting. For this
mode, the platform flash memory controller module simply stalls any read reference until the flash
memory has completed its program/erase operation. If a read access arrives while the array is busy
or if MCR[DONE] goes low while a read is still in progress, the AHB data phase is stalled and the
read access address is saved. Once the array has completed its program/erase operation, the
platform flash memory controller uses the saved address and attribute information to create a
pseudo address phase cycle to “retry” the read reference and sends the registered information to the
array. Once the retried address phase is complete, the read is processed normally and once the data
is valid, it is forwarded to the AHB bus to terminate the system bus transfer.
• BKn_RWWC = 0b110
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