MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 735
Chapter 28
Static RAM (SRAM)
28.1 Introduction
The general-purpose SRAM has a size of 48 KB. In every mode other than STANDBY all the 48 KB of
SRAM are powered, while during STANDBY mode the user can decide to retain 32 KB or just 8 KB. See
the MC_ME chapter in this reference manual for details.
The SRAM provides the following features:
• SRAM can be read/written from any bus master
• Byte, halfword and word addressable
• ECC (error correction code) protected with single-bit correction and double-bit detection
28.2 Low power configuration
In order to reduce leakage a portion of the SRAM can be switched off/unpowered during standby mode.
28.3 Register memory map
The L2SRAM occupies 48 KB of memory starting at the base address as shown in Table 28-2.
The internal SRAM has no registers. Registers for the SRAM ECC are located in the ECSM (see the Error
Correction Status Module (ECSM) chapter of the reference manual for more information).
28.4 SRAM ECC mechanism
The SRAM ECC detects the following conditions and produces the following results:
• Detects and corrects all 1-bit errors
• Detects and flags all 2-bit errors as non-correctable errors
Table 28-1. Low power configuration
Mode Configuration
RUN, TEST, SAFE and
STOP
The entire SRAM is powered and operational.
STANDBY Either 32 KB or just 8 KB of the SRAM remains powered. This option is
software-selectable.
Table 28-2. SRAM memory map
Address Register name Register description Size
0x4000_0000 (Base) — SRA up to 48 KB
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