MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 129
7.6 Functional Description
7.6.1 System Clock Generation
Figure 7-6 shows the block diagram of the system clock generation logic. The MC_ME provides the
system clock select and switch mask (see MC_ME chapter for more details), and the MC_RGM provides
the safe clock request (see MC_RGM chapter for more details). The safe clock request forces the selector
to select the 16 MHz int. RC osc. as the system clock and to ignore the system clock select.
7.6.1.1 System Clock Source Selection
During normal operation, the system clock selection is controlled
• on a SAFE mode or reset event, by the MC_RGM
• otherwise, by the MC_ME
7.6.1.2 System Clock Disable
During normal operation, the system clock can be disabled by the MC_ME.
7.6.1.3 System Clock Dividers
The MC_CGM generates three derived clocks from the system clock.
7.6.1.4 Dividers Functional Description
Dividers are utilized for the generation of divided system and peripheral clocks. The MC_CGM has the
following control registers for built-in dividers:
• Section 7.5.1.4, “System Clock Divider Configuration Registers (CGM_SC_DC0…2)
The reset value of all counters is ‘1’. If a divider has its DE bit in the respective configuration register set
to ‘0’ (the divider is disabled), any value in its DIVn field is ignored.
DIV1 Divider 1 Division Value — The resultant peripheral set 2 clock will have a period DIV1 + 1 times that of
the system clock. If the DE1 is set to ‘0’ (Divider 1 is disabled), any write access to the DIV1 field is ignored
and the peripheral set 2 clock remains disabled.
DE2 Divider 2 Enable
0 Disable system clock divider 2
1 Enable system clock divider 2
DIV2 Divider 2 Division Value — The resultant peripheral set 3 clock will have a period DIV2 + 1 times that of
the system clock. If the DE2 is set to ‘0’ (Divider 2 is disabled), any write access to the DIV2 field is ignored
and the peripheral set 3 clock remains disabled.
Table 7-6. System Clock Divider Configuration Registers (CGM_SC_DC0…2) Field Descriptions (continued)
Field Description
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