MPC5604B/C Microcontroller Reference Manual, Rev. 8
728 Freescale Semiconductor
The second case that can cause an error response to the AHB is when an access is performed to the flash
memory array and is terminated with a flash memory error response. See Section 27.8.7, Flash error
response operation. This may occur for either a read or a write operation.
A third case involves an attempted read access while the flash memory array is busy doing a write
(program) or erase operation if the appropriate read-while-write control field is programmed for this
response. The 3-bit read-while-write control allows for immediate termination of an attempted read, or
various stall-while-write/erase operations are occurring.
27.8.6 Access pipelining
The platform flash memory controller does not support access pipelining since this capability is not
supported by the flash memory array. As a result, the APC (Address Pipelining Control) field should
typically be the same value as the RWSC (Read Wait-State Control) field for best performance, that is,
BKn_APC = BKn_RWSC. It cannot be less than the RWSC.
27.8.7 Flash error response operation
The flash memory array may signal an error response to terminate a requested access with an error. This
may occur due to an uncorrectable ECC error, or because of improper sequencing during program/erase
operations. When an error response is received, the platform flash memory controller does not update or
validate a bank0 page read buffer nor the bank1 temporary holding register. An error response may be
signaled on read or write operations. For additional information on the system registers which capture the
faulting address, attributes, data and ECC information, see the chapter “Error Correction Status Module
(ECSM).”
27.8.8 Bank0 page read buffers and prefetch operation
The logic associated with bank0 of the platform flash memory controller contains four 128-bit page read
buffers which are used to hold instructions and data read from the flash memory array. Each buffer operates
independently, and is filled using a single array access. The buffers are used for both prefetch and normal
demand fetches.
For the general case, a page buffer is written at the completion of an error-free flash memory access and
the valid bit asserted. Subsequent flash memory accesses that “hit” the buffer, that is, the current access
address matches the address stored in the buffer, can be serviced in 0 AHB wait-states as the stored read
data is routed from the given page buffer back to the requesting bus master.
As noted in Section 27.8.7, Flash error response operation”, a page buffer is not marked as valid if the flash
memory array access terminated with any type of transfer error. However, the result is that flash memory
array accesses that are tagged with a single-bit correctable ECC event are loaded into the page buffer and
validated. For additional comments on this topic, see Section 27.8.8.4, Buffer invalidation”.
Prefetch triggering is controllable on a per-master and access-type basis. Bus masters may be enabled or
disabled from triggering prefetches, and triggering may be further restricted based on whether a read
access is for instruction or data. A read access to the platform flash memory controller may trigger a
prefetch to the next sequential page of array data on the first idle cycle following the request. The access
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