MPC5604B/C Microcontroller Reference Manual, Rev. 8
580 Freescale Semiconductor
24.4.5.2.2 Coherent accesses
It is highly recommended that the software waits for a new FLAG set event before start reading
EMIOSA[n] and EMIOSB[n] registers to get a new measurement. The FLAG indicates that new data has
been captured and it is the only way to assure data coherency.
The FLAG set event can be detected by polling the FLAG bit or by enabling the interrupt request or CTU
trigger generation.
Reading the EMIOSA[n] register again in the same period of the last read of EMIOSB[n] register may lead
to incoherent results. This will occur if the last read of EMIOSB[n] register occurred after a disabled B2
to B1 transfer.
24.4.5.2.3 Channel/Modes initialization
The following basic steps summarize basic output mode startup, assuming the channels are initially in
GPIO mode:
1. [global] Disable Global Prescaler.
2. [timebase channel] Disable Channel Prescaler.
3. [timebase channel] Write initial value at internal counter.
4. [timebase channel] Set A/B register.
5. [timebase channel] Set channel to MC(B) Up mode.
6. [timebase channel] Set prescaler ratio.
7. [timebase channel] Enable Channel Prescaler.
8. [output channel] Disable Channel Prescaler.
9. [output channel] Set A/B register.
10. [output channel] Select timebase input through bits BSL[1:0].
11. [output channel] Enter output mode.
12. [output channel] Set prescaler ratio (same ratio as timebase channel).
13. [output channel] Enable Channel Prescaler.
14. [global] Enable Global Prescaler.
15. [global] Enable Global Time Base.
The timebase channel and the output channel may be the same for some applications such as in
OPWFM(B) mode or whenever the output channel is intended to run the timebase itself.
The flags can be configured at any time.
24.5 Periodic Interrupt Timer (PIT)
24.5.1 Introduction
The PIT is an array of timers that can be used to raise interrupts.
Figure 24-56 shows the PIT block diagram.
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