MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 527
24.2.3 Overview of the PIT
The PIT module consists of 6 Periodic Interrupt Timers (PITs) clocked from the system clock.
Out of reset, the PITis disabled. There is a global disable control bit for all of the PIT timers. Before using
the timers, software must clear the appropriate disabled bit. Each of the PIT timers are effectively
standalone entities and each have their own timer and control registers.
The PIT timers are 32-bit count down timers. To use them, you must first program an initial value into the
LDVAL register. The timer will then start to count down and can be read at any time. Once the timer
reaches 0x0000_0000, a flag is set and the previous value is automatically re-loaded into the LDVAL
register and the countdown starts again. The flag event can be routed to a dedicated INTC interrupt if
desired.
The PIT is also used to trigger other events:
• 1 PIT channels can be used to trigger a CTU ADC conversion (single)
• 1 PIT channel can be used to directly trigger injected conversions on the ADC
The timers can be configured to stop (freeze) or to continue to run in debug mode. The PITis available in
all modes where a system clock is generated.
There are no external pins associated with the PIT.
24.3 System Timer Module (STM)
24.3.1 Introduction
24.3.1.1 Overview
The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and
application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare
channels with a separate interrupt source for each channel. The counter is driven by the system clock
divided by an 8-bit prescale value (1 to 256).
24.3.1.2 Features
The STM has the following features:
UC[12] PG[3]
UC[13] PG[4]
UC[14] PG[5]
UC[15] PG[6]
Table 24-2. eMIOS_1 channel to pin mapping (continued)
Channel
Pin function
Channel
Pin function
ALT1 ALT2 ALT3 ALT1 ALT2 ALT3
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