MPC5604B/C Microcontroller Reference Manual, Rev. 8
118 Freescale Semiconductor
6.8.5.6 Measurement Duration Register (CMU_MDR)
FLLI FMPLL clock frequency lower than low reference event.
This bit is set by hardware when f
FMPLL_clk
becomes lower than LFREF value and FMPLL_clk is ‘ON’
as signalled by the MC_ME. It can be cleared by software by writing ‘1’.
0 No FLL event.
1 FLL event is pending.
OLRI Oscillator frequency lower than RC frequency event.
This bit is set by hardware when f
FXOSC_clk
is lower than FIRC_clk/2
RCDIV
frequency and FXOSC_clk
is ‘ON’ as signalled by the MC_ME. It can be cleared by software by writing ‘1’.
0 No OLR event.
1 OLR event is pending.
Offset:
0x18 Access: Read/write
0123456789101112131415
R00000000 0000
MD[19:16]
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MD[15:0]
W
Reset0000000000000000
Figure 6-17. Measurement Duration Register (CMU_MDR)
Table 6-22. CMU_MDR field descriptions
Field Description
MD Measurement duration bits.
This field displays the measurement duration in numbers of clock cycles of the selected clock source.
This value is loaded in the frequency meter downcounter. When CMU_CSR[SFM] = 1, the
downcounter starts counting.
Table 6-21. CMU_ISR field descriptions (continued)
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