MPC5604B/C Microcontroller Reference Manual, Rev. 8
796 Freescale Semiconductor
during the shift-DR state. Both the data capture and the shift operation are transparent to system
operation.
• The PRELOAD part of the instruction initializes the boundary scan register cells before selecting
the EXTEST instructions to perform boundary scan tests. This is achieved by shifting in
initialization data to the boundary scan register during the shift-DR state. The initialization data is
transferred to the parallel outputs of the boundary scan register cells on the falling edge of TCK in
the update-DR state. The data is applied to the external output pins by the EXTEST instruction.
System operation is not affected.
During the SAMPLE/PRELOAD instruction, the following pad status is enforced:
• Weak pull is disabled (independent from PCRx[WPE])
• Analog switch is disabled (independent of PCRx[APC])
• Slew rate control is forced to the slowest configuration (independent from PCRx[SRC[1]])
32.8.5 Boundary Scan
The boundary scan technique allows signals at component boundaries to be controlled and observed
through the shift-register stage associated with each pad. Each stage is part of a larger boundary scan
register cell, and cells for each pad are interconnected serially to form a shift-register chain around the
border of the design. The boundary scan register consists of this shift-register chain, and is connected
between TDI and TDO when the EXTEST, SAMPLE, or SAMPLE/PRELOAD instructions are loaded.
The shift-register chain contains a serial input and serial output, as well as clock and control signals.
32.9 e200z0 OnCE controller
The e200z0 core OnCE controller supports a complete set of Nexus 1 debug features, as well as providing
access to the Nexus2+ configuration registers. A complete discussion of the e200z0 OnCE debug features
is available in the e200z0 Reference Manual.
32.9.1 e200z0 OnCE Controller Block Diagram
Figure 32-6 is a block diagram of the e200z0 OnCE block.
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