MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 167
8.4.2 Modes Details
8.4.2.1 RESET Mode
The device enters this mode on the following events:
• from SAFE, DRUN, RUN0…3, or TEST mode when the TARGET_MODE bit field of the
ME_MCTL register is written with “0000”
• from any mode due to a system reset by the MC_RGM because of some non-recoverable hardware
failure in the system (see the MC_RGM chapter for details)
Transition to this mode is instantaneous, and the system remains in this mode until the reset sequence is
finished. The mode configuration information for this mode is provided by the ME_RESET_MC register.
This mode has a pre-defined configuration, and the 16 MHz int. RC osc. is selected as the system clock.
All power domains are made active in this mode.
8.4.2.2 DRUN Mode
The device enters this mode on the following events.
• automatically from RESET mode after completion of the reset sequence
SAFE
DRUN
TEST
RESET
RUN0
RUN1
HALT
STOP
SYSTEM MODES USER MODES
software
request
non-recoverable
failure
RUN2
RUN3
recoverable
hardware failure
Figure 8-24. MC_ME Mode Diagram
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