MPC5604B/C Microcontroller Reference Manual, Rev. 8
184 Freescale Semiconductor
can only request the SAFE or RESET mode. It is not possible to request any other mode or to go
back to the low-power mode again.
Whenever an invalid mode request is detected, the interrupt pending bit I_IMODE of the ME_IS register
is set, and an interrupt request is generated if the mask bit M_IMODE is ME_IM register is ‘1’.
8.4.5.3 SAFE Mode Transition Interrupt
Whenever the system enters the SAFE mode as a result of a SAFE mode request from the MC_RGM due
to a hardware failure, the interrupt pending bit I_SAFE of the ME_IS register is set, and an interrupt is
generated if the mask bit M_SAFE of ME_IM register is ‘1’.
The SAFE mode interrupt pending bit can be cleared only when the SAFE mode request is deasserted by
the MC_RGM (see the MC_RGM chapter for details on how to clear a SAFE mode request). If the system
is already in SAFE mode, any new SAFE mode request by the MC_RGM also sets the interrupt pending
bit I_SAFE. However, the SAFE mode interrupt pending bit is not set when the SAFE mode is entered by
a software request (i.e. programming of ME_MCTL register).
8.4.5.4 Mode Transition Complete interrupt
Whenever the system completes a mode transition fully (i.e. the S_MTRANS bit of ME_GS register
transits from ‘1’ to ‘0’), the interrupt pending bit I_MTC of the ME_IS register is set, and interrupt request
is generated if the mask bit M_MTC of the ME_IM register is ‘1’. The interrupt bit I_MTC is not set when
entering low-power modes HALT and STOP in order to avoid the same event requesting the exit of these
low-power modes.
8.4.6 Peripheral Clock Gating
During all device modes, each peripheral can be associated with a particular clock gating policy
determined by two groups of peripheral configuration registers.
The run peripheral configuration registers ME_RUN_PC0…7 are chosen only during the software running
modes DRUN, TEST, SAFE, and RUN0…3. All configurations are programmable by software according
to the needs of application. Each configuration register contains a mode bit which determines whether or
not a peripheral clock is to be gated. Run configuration selection for each peripheral is done by the
RUN_CFG bit field of the ME_PCTL0…143 registers.
The low-power peripheral configuration registers ME_LP_PC0…7 are chosen only during the low-power
modes HALT, STOP, and STANDBY. All configurations are programmable by software according to the
needs of the application. Each configuration register contains a mode bit which determines whether or not
a peripheral clock is to be gated. Low-power configuration selection for each peripheral is done by the
LP_CFG bit field of the ME_PCTL0…143 registers.
Any modifications to the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers do not
affect the clock gating behavior until a new mode transition request is generated.
Whenever the processor enters a debug session during any mode, the following occurs for each peripheral:
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