MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 727
Throughout this discussion, bkn_ is used as a prefix to refer to two signals, each for each bank: bk0_ and
bk1_. Also, the nomenclature Bx_Py_RegName is used to reference a program-visible register field
associated with bank “x” and port “y”.
27.8.1 Access protections
The platform flash memory controller provides programmable configurable access protections for both
read and write cycles from masters via the PFlash Access Protection Register (PFAPR). It allows
restriction of read and write requests on a per-master basis. This functionality is described in
Section 27.7.2.2.3, Platform Flash Access Protection Register (PFAPR)”. Detection of a protection
violation results in an error response from the platform flash memory controller on the AHB transfer.
27.8.2 Read cycles – Buffer miss
Read cycles from the flash memory array are initiated by the platform flash memory controller. The
platform flash memory controller then waits for the programmed number of read wait-states before
sampling the read data from the flash memory array. This data is normally stored in the least-recently
updated page read buffer for bank0 in parallel with the requested data being forwarded to the AHB. For
bank1, the data is captured in the page-wide temporary holding register as the requested data is forwarded
to the AHB bus.
If the flash memory access was the direct result of an AHB transaction, the page buffer is marked as
most-recently-used as it is being loaded. If the flash memory access was the result of a speculative prefetch
to the next sequential line, it is first loaded into the least-recently-used buffer. The status of this buffer is
not changed to most-recently-used until a subsequent buffer hit occurs.
27.8.3 Read cycles – Buffer hit
Single cycle read responses to the AHB are possible with the platform flash memory controller when the
requested read access was previously loaded into one of the bank0 page buffers. In these “buffer hit” cases,
read data is returned to the AHB data phase with a zero wait-state response.
Likewise, the bank1 logic includes a single 128-bit temporary holding register and sequential accesses
which “hit” in this register are also serviced with a zero wait-state response.
27.8.4 Write cycles
Write cycles are initiated by the platform flash memory controller. The platform flash memory controller
then waits for the appropriate number of write wait-states before terminating the write operation.
27.8.5 Error termination
The first case that can cause an error response to the AHB is when an access is attempted by an AHB
master whose corresponding Read Access Control or Write Access Control settings do not allow the
access, thus causing a protection violation. In this case, the platform flash memory controller does not
initiate a flash memory array access.
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