Freescale Semiconductor MPC5604B - Application Example

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 185
• The clock is gated if the DBG_F bit of the associated ME_PCTL0…143 register is set. Otherwise,
the peripheral clock gating status depends on the RUN_CFG and LP_CFG bits. Any further
modifications of the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers
during a debug session will take affect immediately without requiring any new mode request.
8.4.7 Application Example
Figure 8-26 shows an example application flow for requesting a mode change and then waiting until the
mode transition has completed.