MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 23
Figure 1-1. Register figure conventions
The numbering of register bits and fields on MPC5604B is as follows:
• Register bit numbers, shown at the top of each figure, use the standard Power Architecture bit
ordering (0, 1, 2, ...) where bit 0 is the most significant bit (MSB).
• Multi-bit fields within a register use conventional bit ordering (..., 2, 1, 0) where bit 0 is the least
significant bit (LSB).
1.5 References
In addition to this reference manual, the following documents provide additional information on the
operation of the MPC5604B:
• IEEE-ISTO 5001-2003 Standard for a Global Embedded Processor Interface (Nexus)
• IEEE 1149.1-2001 standard - IEEE Standard Test Access Port and Boundary-Scan Architecture
• Power Architecture Book E V1.0
(http://www.freescale.com/files/32bit/doc/user_guide/BOOK_EUM.pdf)
1.6 How to use the MPC5604B documents
This section:
• Describes how the MPC5604B documents provide information on the microcontroller
• Makes recommendations on how to use the documents in a system design
1.6.1 The MPC5604B document set
The MPC5604B document set comprises:
• This reference manual (provides information on the features of the logical blocks on the device and
how they are integrated with each other)
• The device data sheet (specifies the electrical characteristics of the device)
• The device product brief
The following reference documents (available online at www.freescale.com) are also available to support
the CPU on this device:
R0 1
W
R FIELD1 FIELD2
W
R
FIELD
W
Reserved bits Read-only fields Read/write fields
RFIELD
Ww1c
Write 1 to clear field
(field will always read 0)
R0 00
W FIELD1 FIELD2
Write-only fields
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