MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 783
31.4.2.7.12 Platform RAM ECC Data Register (PREDR)
The PREDR is a 32-bit register for capturing the data associated with the last, properly-enabled ECC event
in the SRAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the
SRAM causes the address, attributes and data associated with the access to be loaded into the PREAR,
PRESR, PREMR, PREAT and PREDR registers, and the appropriate flag (R1BC or RNCE) in the ECC
Status Register to be asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
31.4.3 Register protection
Logic exists which restricts accesses to INTC, ECSM, MPU, STM and SWT to supervisor mode only.
Accesses in User mode are not possible.
Offset: 0x6C Access: Read
0123456789101112131415
R REDR[31:16]
W
Reset:––––––––––––––––
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RREDR[15:0]
W
Reset:––––––––––––––––
Figure 31-18. Platform RAM ECC Data Register (PREDR)
Table 31-20. PREDR field descriptions
Field Description
REDR SRAM ECC Data Register
This 32-bit register contains the data associated with the faulting access of the last, properly-enabled
SRAM ECC event. The register contains the data value taken directly from the data bus.
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