MPC5604B/C Microcontroller Reference Manual, Rev. 8
310 Freescale Semiconductor
18.5.2 Register description
18.5.2.1 MPU Control/Error Status Register (MPU_CESR)
The MPU_CESR provides one byte of error status plus three bytes of configuration information. A global
MPU enable/disable bit is also included in this register.
Table 18-1. MPU memory map
Base address: 0xFFF1_1000
Address offset Register Location
0x000 MPU Control/Error Status Register (MPU_CESR) on page 310
0x004–0x00F
Reserved
0x010 MPU Error Address Register, Slave Port 0 (MPU_EAR0) on page 311
0x014 MPU Error Detail Register, Slave Port 0 (MPU_EDR0) on page 312
0x018 MPU Error Address Register, Slave Port 1 (MPU_EAR1) on page 311
0x01C MPU Error Detail Register, Slave Port 1 (MPU_EDR1) on page 312
0x020 MPU Error Address Register, Slave Port 2 (MPU_EAR2) on page 311
0x024 MPU Error Detail Register, Slave Port 2 (MPU_EDR2) on page 312
0x028–0x3FF Reserved
0x400 MPU Region Descriptor 0 (MPU_RGD0) on page 314
0x410 MPU Region Descriptor 1 (MPU_RGD1) on page 314
0x420 MPU Region Descriptor 2 (MPU_RGD2) on page 314
0x430 MPU Region Descriptor 3 (MPU_RGD3) on page 314
0x440 MPU Region Descriptor 4 (MPU_RGD4) on page 314
0x450 MPU Region Descriptor 5 (MPU_RGD5) on page 314
0x460 MPU Region Descriptor 6 (MPU_RGD6) on page 314
0x470 MPU Region Descriptor 7 (MPU_RGD7) on page 314
0x480–0x7FF Reserved
0x800 MPU RGD Alternate Access Control 0 (MPU_RGDAAC0) on page 319
0x804 MPU RGD Alternate Access Control 1 (MPU_RGDAAC1) on page 319
0x808 MPU RGD Alternate Access Control 2 (MPU_RGDAAC2) on page 319
0x80C MPU RGD Alternate Access Control 3 (MPU_RGDAAC3) on page 319
0x810 MPU RGD Alternate Access Control 4 (MPU_RGDAAC4) on page 319
0x814 MPU RGD Alternate Access Control 5 (MPU_RGDAAC5) on page 319
0x818 MPU RGD Alternate Access Control 6 (MPU_RGDAAC6) on page 319
0x81C MPU RGD Alternate Access Control 7 (MPU_RGDAAC7) on page 319
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