Freescale Semiconductor MPC5604B - Chapter 12; NMI Status Flag Register (NSR)

MPC5604B/C Microcontroller Reference Manual, Rev. 8
232 Freescale Semiconductor
NOTE
Reserved registers will read as 0, writes will have no effect. If
SSCM_ERROR[RAE] is enabled, a transfer error will be issued when
trying to access completely reserved register space.
12.4.2 NMI Status Flag Register (NSR)
This register holds the non-maskable interrupt status flags.
Table 12-2. WKPU memory map
Base address: 0xC3F9_4000
Address offset Register name Location
0x00 NMI Status Flag Register (NSR) on page 232
0x04 – 0x07
Reserved
0x08 NMI Configuration Register (NCR) on page 233
0x0C – 0x13 Reserved
0x14 Wakeup/Interrupt Status Flag Register (WISR) on page 234
0x18 Interrupt Request Enable Register (IRER) on page 235
0x1C Wakeup Request Enable Register (WRER) on page 235
0x20 – 0x27 Reserved
0x28 Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER) on page 236
0x2C Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER) on page 236
0x30 Wakeup/Interrupt Filter Enable Register (WIFER) on page 237
0x34 Wakeup/Interrupt Pullup Enable Register (WIPUER) on page 237
Offset: 0x00 Access: User read/write
0123456789101112131415
R
NIF0
NOVF0
00000000000000
Ww1c w1c
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W
Reset0000000000000000
Figure 12-2. NMI Status Flag Register (NSR)