MPC5604B/C Microcontroller Reference Manual, Rev. 8
464 Freescale Semiconductor
A direct consequence of the first requirement is that the minimum number of time quanta per CAN bit must
be 8, so the oscillator clock frequency should be at least 8 times the CAN bit rate. The minimum frequency
ratio specified in Table 22-21 can be achieved by choosing a high enough peripheral clock frequency when
compared to the oscillator clock frequency, or by adjusting one or more of the bit timing parameters
(PRESDIV, PROPSEG, PSEG1, PSEG2). As an example, taking the case of 64 MBs, if the oscillator and
peripheral clock frequencies are equal and the CAN bit timing is programmed to have 8 time quanta per
bit, then the prescaler factor (PRESDIV + 1) should be at least 2. For prescaler factor equal to one and
CAN bit timing with 8 time quanta per bit, the ratio between peripheral and oscillator clock frequencies
should be at least 2.
22.4.10 Modes of operation details
22.4.10.1 Freeze Mode
This mode is entered by asserting the HALT bit in the MCR or when the MCU is put into Debug Mode.
In both cases it is also necessary that the FRZ bit is asserted in the MCR and the module is not in low power
mode (Disable Mode). When Freeze Mode is requested during transmission or reception, FlexCAN does
the following:
• Waits to be in either Intermission, Passive Error, Bus Off or Idle state
• Waits for all internal activities like arbitration, matching, move-in and move-out to finish
• Ignores the Rx input pin and drives the Tx pin as recessive
• Stops the prescaler, thus halting all CAN protocol activities
• Grants write access to the Error Counters Register, which is read-only in other modes
• Sets the NOT_RDY and FRZ_ACK bits in MCR
After requesting Freeze Mode, the user must wait for the FRZ_ACK bit to be asserted in MCR before
executing any other action, otherwise FlexCAN may operate in an unpredictable way. In Freeze mode, all
memory mapped registers are accessible.
Exiting Freeze Mode is done in one of the following ways:
• CPU negates the FRZ bit in the MCR
• The MCU is removed from Debug Mode and/or the HALT bit is negated
Once out of Freeze Mode, FlexCAN tries to resynchronize to the CAN bus by waiting for 11 consecutive
recessive bits.
22.4.10.2 Module Disable Mode
This low power mode is entered when the MDIS bit in the MCR is asserted. If the module is disabled
during Freeze Mode, it shuts down the clocks to the CPI and MBM submodules, sets the LPM_ACK bit
and negates the FRZ_ACK bit. If the module is disabled during transmission or reception, FlexCAN does
the following:
• Waits to be in either Idle or Bus Off state, or else waits for the third bit of Intermission and then
checks it to be recessive
To Next Page
Loading...
