Freescale Semiconductor MPC5604B - Interrupt Requests

MPC5604B/C Microcontroller Reference Manual, Rev. 8
514 Freescale Semiconductor
23.6.7 Interrupt requests
The DSPI has five conditions that can generate interrupt requests.
Table 23-32 lists the five conditions.
Each condition has a flag bit and a request enable bit. The flag bits are described in the Section 23.5.5,
DSPI Status Register (DSPIx_SR) and the request enable bits are described in the Section 23.5.6, DSPI
Interrupt Request Enable Register (DSPIx_RSER). The TX FIFO fill flag (TFFF) and RX FIFO drain flag
(RFDF) generate interrupt requests depending on the TFFF_DIRS and RFDF_DIRS bits in the
DSPIx_RSER.
23.6.7.1 End of Queue Interrupt Request (EOQF)
The end of queue request indicates that the end of a transmit queue is reached. The end of queue request
is generated when the EOQ bit in the executing SPI command is asserted and the EOQF_RE bit in the
DSPIx_RSER is set. See the EOQ bit description in Section 23.5.5, DSPI Status Register (DSPIx_SR). See
Figure 23-16 and Figure 23-17 that illustrate when EOQF is set.
23.6.7.2 Transmit FIFO Fill Interrupt Request (TFFF)
The transmit FIFO fill request indicates that the TX FIFO is not full. The transmit FIFO fill request is
generated when the number of entries in the TX FIFO is less than the maximum number of possible entries,
and the TFFF_RE bit in the DSPIx_RSER is set. The TFFF_DIRS bit in the DSPIx_RSER is used to
generate an interrupt request.
23.6.7.3 Transfer Complete Interrupt Request (TCF)
The transfer complete request indicates the end of the transfer of a serial frame. The transfer complete
request is generated at the end of each frame transfer when the TCF_RE bit is set in the DSPIx_RSER. See
the TCF bit description in Section 23.5.5, DSPI Status Register (DSPIx_SR). See Figure 23-16 and
Figure 23-17 that illustrate when TCF is set.
Table 23-32. Interrupt request conditions
Condition Flag
End of transfer queue has been reached (EOQ) EOQF
Current frame transfer is complete TCF
TX FIFO underflow has occurred TFUF
RX FIFO overflow occurred RFOF
A FIFO overrun occurred
1
1
The FIFO overrun condition is created by ORing the TFUF and RFOF flags together.
TFUF ORed with RFOF