MPC5604B/C Microcontroller Reference Manual, Rev. 8
642 Freescale Semiconductor
The hardware algorithm performs the steps necessary to ensure that the storage elements are programmed
and erased with sufficient margin to guarantee data integrity and reliability.
In the flash memory module, logic levels are defined as follows:
• A programmed bit reads as logic level 0 (or low).
• An erased bit reads as logic level 1 (or high).
Program and erase of the flash memory module requires multiple system clock cycles to complete.
The erase sequence may be suspended.
The program and erase sequences may be aborted.
27.4.2 Flash memory module sectorization
27.4.2.1 CFlash module sectorization
The CFlash module supports 512 KBof user memory, plus 16 KB of test memory (a portion of which is
One-Time Programmable by the user). An extra 16 KB sector is available as Shadow space usable for user
option bits and censorship settings.
The module is composed of a single bank (Bank 0): Read-While-Write is not supported.
Bank 0 of the module is divided in 10 sectors including a reserved sector, named TestFlash, in which some
One-Time Programmable (OTP) user data are stored, as well as a Shadow Sector in which user erasable
configuration values can be stored.
The matrix module sectorization is shown in Table 27-2.
Table 27-2. CFlash module sectorization
Bank Sector Addresses Size (KB)
Address
space
CFLASH_LML field for
locking the address space
0 0 0x00000000–0x00007FFF 32
Low
LLK0
1 0x00008000–0x0000BFFF 16 LLK1
2 0x0000C000–0x0000FFFF 16 LLK2
3 0x00010000–0x00017FFF 32 LLK3
4 0x00018000–0x0001FFFF 32 LLK4
5 0x00020000–0x0003FFFF 128 LLK5
6 0x00040000–0x0005FFFF 128
Mid
MLK0
7 0x00060000–0x0007FFFF 128 MLK1
Shadow 0x00200000–0x00203FFF 16 Shadow TSLK
Test 0x00400000–0x00403FFF 16 Test TSLK
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