MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 189
• short reset sequence configuration
• bidirectional reset behavior configuration
• selection of alternate boot via the backup SRAM on STANDBY mode exit (for further mode
details, please see the MC_ME chapter)
• boot mode capture on RESET deassertion
9.1.3 Modes of operation
The different reset sources are organized into two families: ‘destructive’ and ‘functional’.
• A ‘destructive’ reset source is associated with an event related to a critical - usually hardware -
error or dysfunction. When a ‘destructive’ reset event occurs, the full reset sequence is applied to
the device starting from PHASE0. This resets the full device ensuring a safe start-up state for both
digital and analog modules. ‘Destructive’ resets are
– power-on reset
– 1.2 V low-voltage detected (power domain #0)
– 1.2 V low-voltage detected (power domain #1)
– software watchdog timer
– 2.7 V low-voltage detected
• A ‘functional’ reset source is associated with an event related to a less-critical - usually
non-hardware - error or dysfunction. When a ‘functional’ reset event occurs, a partial reset
sequence is applied to the device starting from PHASE1. In this case, most digital modules are reset
normally, while analog modules or specific digital modules’ (e.g. debug modules, flash modules)
state is preserved. ‘Functional’ resets are
– external reset
– JTAG initiated reset
– debug control core reset
– software reset
– checkstop reset
– FMPLL fail
– FXOSC frequency lower than reference
– CMU clock frequency higher/lower than reference
– 4.5 V low-voltage detected
– code or data flash fatal error
When a reset is triggered, the MC_RGM state machine is activated and proceeds through the different
phases (i.e. PHASEn states). Each phase is associated with a particular device reset being provided to the
system. A phase is completed when all corresponding phase completion gates from either the system or
internal to the MC_RGM are acknowledged. The device reset associated with the phase is then released,
and the state machine proceeds to the next phase up to entering the IDLE phase. During this entire process,
the MC_ME state machine is held in RESET mode. Only at the end of the reset sequence, when the IDLE
phase is reached, does the MC_ME enter the DRUN mode.
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