MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 265
• 32-bit single cycle barrel shifter for shifts and rotates
• 32-bit mask unit for data masking and insertion
• Divider logic for signed and unsigned divide in 5 to 34 clocks with minimized execution timing
• 8x32 hardware multiplier array supports 1 to 4 cycle 32x32->32 multiply (early out)
15.4.3 Load/Store unit features
The e200 load/store unit supports load, store, and the load multiple / store multiple instructions:
• 32-bit effective address adder for data memory address calculations
• Pipelined operation supports throughput of one load or store operation per cycle
• 32-bit interface to memory (dedicated memory interface on e200z0h)
15.4.4 e200z0h system bus features
The features of the e200z0h system bus interface are as follows:
• Independent instruction and data buses
•AMBA
1
AHB
2
Lite Rev 2.0 specification with support for ARM v6 AMBA extensions
— Exclusive access monitor
— Byte lane strobes
— Cache allocate support
• 32-bit address bus plus attributes and control on each bus
• 32-bit read data bus for instruction interface
• Separate uni-directional 32-bit read data bus and 32-bit write data bus for data interface
• Overlapped, in-order accesses
15.4.5 Nexus 2+ features
The Nexus 2+ module is compliant with Class 2 of the IEEE-ISTO 5001-2003 standard, with additional
Class 3 and Class 4 features available. The following features are implemented:
• Program Trace via Branch Trace Messaging (BTM)—Branch trace messaging displays program
flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool
to interpolate what transpires between the discontinuities. Thus, static code may be traced.
• Ownership Trace via Ownership Trace Messaging (OTM)—OTM facilitates ownership trace by
providing visibility of which process ID or operating system task is activated. An Ownership Trace
Message is transmitted when a new process/task is activated, allowing the development tool to
trace ownership flow.
• Run-time access to the processor memory map via the JTAG port. This allows for enhanced
download/upload capabilities.
• Watchpoint Messaging via the auxiliary interface
1. Advanced Microcontroller Bus Architecture
2. Advanced High Performance Bus
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