Freescale Semiconductor MPC5604B - Interrupt Registers

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 611
25.4.3 Interrupt registers
25.4.3.1 Interrupt Status Register (ISR)
The Interrupt Status Register (ISR) contains interrupt status bits for the ADC.
25.4.3.2 Channel Pending Registers (CEOCFR[0..2])
CEOCFR0 = End of conversion pending interrupt for channel 0 to 15 (precision channels)
CEOCFR1 = End of conversion pending interrupt for channel 32 to 47 (standard channels)
CEOCFR2 = End of conversion pending interrupt for channel 64 to 95 (external multiplexed channels)
Address: Base + 0x0010 Access: User read/write
0123456789101112131415
R00000000 00000 000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0000000
0 000
EO
CTU
JEOC JECH
EOC ECH
W
w1c w1c w1c w1c w1c
Reset0000000000000000
Figure 25-10. Interrupt Status Register (ISR)
Table 25-9. ISR field descriptions
Field Description
EOCTU End of CTU Conversion interrupt flag
When this bit is set, an EOCTU interrupt has occurred.
JEOC End of Injected Channel Conversion interrupt flag
When this bit is set, a JEOC interrupt has occurred.
JECH End of Injected Chain Conversion interrupt flag
When this bit is set, a JECH interrupt has occurred.
EOC End of Channel Conversion interrupt flag
When this bit is set, an EOC interrupt has occurred.
ECH End of Chain Conversion interrupt flag
When this bit is set, an ECH interrupt has occurred.