MPC5604B/C Microcontroller Reference Manual, Rev. 8
226 Freescale Semiconductor
4. LV (low voltage internal power supply for core, FMPLL and Flash digital logic) — This is
generated internally by embedded voltage regulator and provided to the core, FMPLL and Flash.
Three VDD_LV/VSS_LV pins pairs are provided to connect the three decoupling capacitances.
This is generated internally by internal voltage regulator but provided outside to connect stability
capacitor. Refer to data sheet for details.
The four dedicated supply domains are further divided within the package in order to reduce as much as
possible EMC and noise issues.
• HV_IO: High voltage pad supply
• HV_FLAn: High voltage Flash supply
• HV_OSC0REG
1
: High voltage external oscillator and regulator supply
• HV_ADR: High voltage reference for ADC module. Supplies are further star routed to reduce
impact of ADC resistive reference on ADC capacitive reference accuracy.
• HV_ADV: High voltage supply for ADC module
• BV: High voltage supply for voltage regulator ballast. These two ballast pads are used to supply
core and Flash. Each pad contains two ballasts to supply 80 mA and 20 mA respectively. Core is
hence supplied through two ballasts of 80 mA capability and CFlash and DFlash through two
20 mA ballasts. The HV supply for both ballasts is shorted through double bonding.
• LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through
double bonding.
• LV_FLAn: Low voltage supply for Flash module n. It is supplied with dedicated ballast and
shorted to LV_COR through double bonding.
•LV_PLL
2
: Low voltage supply for FMPLL
11.3 Power domain organization
Based on stringent requirements for current consumption in different operational modes, the device is
partitioned into different power domains. Organization into these power domains primarily means separate
power supplies which are separated from each other by use of power switches (switch SW1 for power
domain No. 1 and switch SW2 for power domain No. 2 as shown in Figure 11-2). These different separated
power supplies are hence enabling to switch off power to certain regions of the device to avoid even
leakage current consumption in logic supplied by the corresponding power supply.
This device employs three primary power domains, namely PD0, PD1 and PD2.
As PCU supports dynamic power down of domains based on different device mode, such a possible
domain is depicted below in dotted periphery.
Power domain organization and connections to the internal regulator are depicted in Figure 11-2.
1. Regulator ground is separated from oscillator ground and shorted to the LV ground through star routing
2. During production test, it is also possible to provide the VDD_LV externally through pins by configuring regulator in bypass
mode.
To Next Page
Loading...
