Freescale Semiconductor MPC5604B - RTC Control Register (RTCC)

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 247
13.5.2 RTC Control Register (RTCC)
The RTCC register contains:
• RTC counter enable
• RTC interrupt enable
• RTC clock source select
• RTC compare value
•API enable
• API interrupt enable
• API compare value
Offset: 0x4 Access: User read/write
0123 4 56789101112131415
R
CNTEN
RTCIE
FRZEN
ROVREN
RTCVAL
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
APIEN
APIIE
CLKSEL
DIV512EN
DIV32EN
APIVAL
W
Reset0000000000000000
Figure 13-4. RTC Control Register (RTCC)
Table 13-3. RTCC field descriptions
Field Description
CNTEN Counter Enable
The CNTEN field enables the RTC counter. Making CNTEN bit 1’b0 has the effect of
asynchronously resetting (synchronous reset negation) all the RTC and API logic. This allows for
the RTC configuration and clock source selection to be updated without causing synchronization
issues.
1 Counter enabled
0 Counter disabled
RTCIE RTC Interrupt Enable
The RTCIE field enables interrupts requests to the system if RTCF is asserted.
1 RTC interrupts enabled
0 RTC interrupts disabled
FRZEN Freeze Enable
The counter freezes on entering the debug mode on the last valid count value if the FRZEN bit is
set. After coming out of the debug mode, the counter starts from the frozen value.
0 Counter does not freeze in debug mode.
1 Counter freezes in debug mode.