MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 465
• Waits for all internal activities like arbitration, matching, move-in and move-out to finish
• Ignores its Rx input pin and drives its Tx pin as recessive
• Shuts down the clocks to the CPI and MBM submodules
• Sets the NOT_RDY and LPM_ACK bits in MCR
The Bus Interface Unit continues to operate, enabling the CPU to access memory mapped registers, except
the Free Running Timer, the Error Counter Register and the Message Buffers, which cannot be accessed
when the module is in Disable Mode. Exiting from this mode is done by negating the MDIS bit, which will
resume the clocks and negate the LPM_ACK bit.
22.4.11 Interrupts
The module can generate up to 69 interrupt sources (64 interrupts due to message buffers and 5 interrupts
due to Ored interrupts from MBs, Bus Off, Error, Tx Warning and Rx Warning). The number of actual
sources depends on the configured number of Message Buffers.
Each one of the message buffers can be an interrupt source, if its corresponding IMASK bit is set. There
is no distinction between Tx and Rx interrupts for a particular buffer, under the assumption that the buffer
is initialized for either transmission or reception. Each of the buffers has assigned a flag bit in the IFLAG
Registers. The bit is set when the corresponding buffer completes a successful transmission/reception and
is cleared when the CPU writes it to ‘1’ (unless another interrupt is generated at the same time).
NOTE
It must be guaranteed that the CPU only clears the bit causing the current
interrupt. For this reason, bit manipulation instructions (BSET) must not be
used to clear interrupt flags. These instructions may cause accidental
clearing of interrupt flags which are set after entering the current interrupt
service routine.
If the Rx FIFO is enabled (bit FEN on MCR set), the interrupts corresponding to MBs 0 to 7 have a
different behavior. Bit 7 of the IFLAG1 becomes the “FIFO Overflow” flag; bit 6 becomes the FIFO
Warning flag, bit 5 becomes the “Frames Available in FIFO flag” and bits 4–0 are unused. See
Section 22.3.4.12, “Interrupt Flags 1 Register (IFLAG1) for more information.
A combined interrupt for all MBs is also generated by an Or of all the interrupt sources from MBs. This
interrupt gets generated when any of the MBs generates an interrupt. In this case the CPU must read the
IFLAG Registers to determine which MB caused the interrupt.
The other 4 interrupt sources (Bus Off, Error, Tx Warning and Rx Warning) generate interrupts like the
MB ones, and can be read from the Error and Status Register. The Bus Off, Error, Tx Warning and Rx
Warning interrupt mask bits are located in the Control Register, and the Wake-Up interrupt mask bit is
located in the MCR.
22.4.12 Bus interface
The CPU access to FlexCAN registers are subject to the following rules:
• Read and write access to supervisor registers in User Mode results in access error.
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