MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 471
– End of queue reached (EOQF)
– TX FIFO is not full (TFFF)
– Transfer of current frame complete (TCF)
– RX FIFO is not empty (RFDF)
– FIFO overrun (attempt to transmit with an empty TX FIFO or serial frame received while
RX FIFO is full) (RFOF) or (TFUF)
• Modified SPI transfer formats for communication with slower peripheral devices
• Supports all functional modes from QSPI subblock of QSMCM (MPC500 family)
• Continuous serial communications clock (SCK)
23.3 Modes of operation
The DSPI has four modes of operation. These modes can be divided into two categories:
• Module-specific: Master, Slave, and Module Disable modes
• MCU-specific: Debug mode
The module-specific modes are entered by host software writing to a register. The MCU-specific mode is
controlled by signals external to the DSPI. An MCU-specific mode is a mode that the entire device may
enter, in parallel to the DSPI being in one of its module-specific modes.
23.3.1 Master mode
Master mode allows the DSPI to initiate and control serial communication. In this mode the SCK, CSn and
SOUT signals are controlled by the DSPI and configured as outputs.
For more information, see Section 23.6.1.1, Master mode.
23.3.2 Slave mode
Slave mode allows the DSPI to communicate with SPI bus masters. In this mode the DSPI responds to
externally controlled serial transfers. The DSPI cannot initiate serial transfers in slave mode. In slave
mode, the SCK signal and the CS0_x signal are configured as inputs and provided by a bus master. CS0_x
must be configured as input and pulled high. If the internal pullup is being used then the appropriate bits
in the relevant SIU_PCR must be set (SIU_PCR [WPE = 1], [WPS = 1]).
For more information, see Section 23.6.1.2, Slave mode.
23.3.3 Module Disable mode
The module disable mode is used for MCU power management. The clock to the non-memory mapped
logic in the DSPI is stopped while in module disable mode. The DSPI enters the module disable mode
when the MDIS bit in DSPIx_MCR is set.
For more information, see Section 23.6.1.3, Module Disable mode.
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