MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 273
16.5.2 Register description
With exception of the INTC_SSCIn and INTC_PSRn, all registers are 32 bits in width. Any combination
of accessing the four bytes of a register with a single access is supported, provided that the access does not
cross a register boundary. These supported accesses include types and sizes of eight bits, aligned 16 bits,
misaligned 16 bits to the middle two bytes, and aligned 32 bits.
Although INTC_SSCIn and INTC_PSRn are 8 bits wide, they can be accessed with a single 16-bit or
32-bit access, provided that the access does not cross a 32-bit boundary.
In software vector mode, the side effects of a read of INTC_IACKR are the same regardless of the size of
the read. In either software or hardware vector mode, the size of a write to either
INTC_SSCIR0_3–INTC_SSCIR4_7 or INTC_EOIR does not affect the operation of the write.
16.5.2.1 INTC Module Configuration Register (INTC_MCR)
The module configuration register is used to configure options of the INTC.
Table 16-2. INTC memory map
Base address: 0xFFF4_8000
Address offset Register Location
0x0000 INTC Module Configuration Register (INTC_MCR) on page 273
0x0004 Reserved
0x0008 INTC Current Priority Register for Processor (INTC_CPR) on page 274
0x000C Reserved
0x0010 INTC Interrupt Acknowledge Register (INTC_IACKR) on page 276
0x0014 Reserved
0x0018 INTC End-of-Interrupt Register (INTC_EOIR) on page 277
0x001C Reserved
0x0020–0x0027 INTC Software Set/Clear Interrupt Registers
(INTC_SSCIR0_3–INTC_SSCIR4_7)
on page 277
0x0028–0x003C Reserved
0x0040–0x00D0 INTC Priority Select Registers
(INTC_PSR0_3–INTC_PSR208_210)
1
1
The PRI fields are “reserved” for peripheral interrupt requests whose vectors are labeled ‘Reserved’ in Figure 16-3.
on page 279
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