MPC5604B/C Microcontroller Reference Manual, Rev. 8
276 Freescale Semiconductor
16.5.2.3 INTC Interrupt Acknowledge Register (INTC_IACKR)
The interrupt acknowledge register provides a value which can be used to load the address of an ISR from
a vector table. The vector table can be composed of addresses of the ISRs specific to their respective
interrupt vectors.
Offset: 0x0010 Access: User read/write
0123456789101112131415
R
VTBA[20:5]
W
Reset
0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
VTBA[4:0]
INTVEC 0 0
W
Reset
0000000000000000
Figure 16-4. INTC Interrupt Acknowledge Register (INTC_IACKR) when INTC_MCR[VTES] = 0
Offset: 0x0010 Access: User read/write
0123456789101112131415
R
VTBA[19:4]
W
Reset
0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
VTBA[3:0]
INTVEC 0 0 0
W
Reset
0000000000000000
Figure 16-5. INTC Interrupt Acknowledge Register (INTC_IACKR) when INTC_MCR[VTES] = 1
Table 16-6. INTC_IACKR field descriptions
Field Description
VTBA Vector Table Base Address
Can be the base address of a vector table of addresses of ISRs.
INTVEC Interrupt Vector
It is the vector of the peripheral or software configurable interrupt request that caused the interrupt
request to the processor. When the interrupt request to the processor asserts, the INTVEC is updated,
whether the INTC is in software or hardware vector mode.
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