MPC5604B/C Microcontroller Reference Manual, Rev. 8
730 Freescale Semiconductor
27.8.8.2 Per-master prefetch triggering
Prefetch triggering may be also controlled for individual bus masters. See Section 27.7.2.2.3, Platform
Flash Access Protection Register (PFAPR), for details on these controls.
27.8.8.3 Buffer allocation
Allocation of the line read buffers is controlled via page buffer configuration (Bx_Py_BCFG) field. This
field defines the operating organization of the four page buffers. The buffers can be organized as a “pool”
of available resources (with all four buffers in the pool) or with a fixed partition between buffers allocated
to instruction or data accesses. For the fixed partition, two configurations are supported. In one
configuration, buffers 0 and 1 are allocated for instruction fetches and buffers 2 and 3 for data accesses. In
the second configuration, buffers 0, 1 and 2 are allocated for instruction fetches and buffer 3 reserved for
data accesses.
27.8.8.4 Buffer invalidation
The page read buffers may be invalidated under hardware or software control.
At the beginning of all program/erase operations, the flash memory array will invalidate the page read
buffers. Buffer invalidation occurs at the next AHB non-sequential access boundary, but does not affect a
burst from a page read buffer which is in progress.
Software may invalidate the buffers by clearing the Bx_Py_BFE bit, which also disables the buffers.
Software may then re-assert the Bx_Py_BFE bit to its previous state, and the buffers will have been
invalidated.
One special case needing software invalidation relates to page buffer “hits” on flash memory data which
was tagged with a single-bit ECC event on the original array access. Recall that the page buffer structure
includes an status bit signaling the array access detected and corrected a single-bit ECC error. On all
subsequent buffer hits to this type of page data, a single-bit ECC event is signaled by the platform flash
memory controller. Depending on the specific hardware configuration, this reporting of a single-bit ECC
event may generate an ECC alert interrupt. In order to prevent repeated ECC alert interrupts, the page
buffers need to be invalidated by software after the first notification of the single-bit ECC event.
Finally, the buffers are invalidated by hardware on any non-sequential access with a non-zero value on
haddr[28:24] to support wait-state emulation.
27.8.9 Bank1 Temporary Holding Register
Recall the bank1 logic within the platform flash memory controller includes a single 128-bit data register,
used for capturing read data. Since this bank does not support prefetching, the read data for the referenced
address is bypassed directly back to the AHB data bus. The page is also loaded into the temporary data
register and subsequent accesses to this page can hit from this register, if it is enabled (B1_P0_BFE).
For the general case, a temporary holding register is written at the completion of an error-free flash
memory access and the valid bit asserted. Subsequent flash memory accesses that “hit” the buffer, that is,
the current access address matches the address stored in the temporary holding register, can be serviced in
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