MPC5604B/C Microcontroller Reference Manual, Rev. 8
724 Freescale Semiconductor
27.7.2.2.3 Platform Flash Access Protection Register (PFAPR)
The PFlash Access Protection Register (PFAPR) is used to control read and write accesses to the flash
memory based on system master number. Prefetching capabilities are defined on a per master basis. This
register also defines the arbitration mode for controllers supporting two AHB ports. The register is
described below in Figure 27-41 and Table 27-60.
The contents of the register are loaded from location 0x203E00 of the shadow region in the code flash
memory (bank0) array at reset. To temporarily change the values of any of the fields in the PFAPR, a write
to the IPS-mapped register is performed. To change the values loaded into the PFAPR at reset, the word
location at address 0x203E00 of the shadow region in the flash memory array must be programmed using
the normal sequence of operations. The reset value shown in Table 27-41 reflects an erased or
unprogrammed value from the shadow region.
BK1_RWWC Bank1 Read-While-Write Control
This 3-bit field defines the controller response to flash memory reads while the array is busy with a
program (write) or erase operation.
0––: Terminate any attempted read while write/erase with an error response
111: Generate a bus stall for a read while write/erase, disable the stall notification interrupt, disable
the abort + abort notification interrupt
110: Generate a bus stall for a read while write/erase, enable the stall notification interrupt, disable
the abort + abort notification interrupt
101: Generate a bus stall for a read while write/erase, enable the operation abort, disable the abort
notification interrupt
100: Generate a bus stall for a read while write/erase, enable the operation abort and the abort
notification interrupt
This field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the
abort and notification interrupts.
This field is ignored in single bank flash memory configurations.
B1_P0_PFE Bank1, Port 0 Buffer Enable
This bit enables or disables read hits from the 128-bit holding register. It is also used to invalidate
the contents of the holding register. This bit is set by hardware reset, enabling the use of the holding
register.
0: The holding register is disabled from satisfying read requests.
1: The holding register is enabled to satisfy read requests on hits.
Table 27-59. PFCR1 field descriptions (continued)
Field Description
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