MPC5604B/C Microcontroller Reference Manual, Rev. 8
272 Freescale Semiconductor
16.4.1.2 Hardware vector mode
In hardware vector mode, the hardware is the interrupt vector signal from the INTC in conjunction with a
processor with the capability use that vector. In hardware vector mode, this hardware causes the first
instruction to be executed in handling the interrupt request to the processor to be specific to that vector.
Therefore the interrupt exception handler is specific to a peripheral or software configurable interrupt
request rather than being common to all of them. The INTC uses hardware vector mode for a given
processor when the associated HVEN bit in the INTC_MCR is asserted. The hardware vector enable signal
to the associated processor is driven as asserted. When the interrupt request to the associated processor
asserts, the interrupt vector signal is updated. The value of that interrupt vector is the unique vector
associated with the preempting peripheral or software configurable interrupt request. The vector value
matches the value of the INTVEC field in the INTC_IACKR field in the INTC_IACKR, depending on
which processor was assigned to handle a given interrupt source.
The processor negates the interrupt request to the processor driven by the INTC by asserting the interrupt
acknowledge signal for one clock. Even if a higher priority interrupt request arrived while waiting for the
interrupt acknowledge, the interrupt request to the processor will negate for at least one clock.
The assertion of the interrupt acknowledge signal for a given processor pushes the associated PRI value in
the associated INTC_CPR register onto the associated LIFO and updates the associated PRI in the
associated INTC_CPR register with the new priority. This pushing of the PRI value onto the associated
LIFO and updating PRI in the associated INTC_CPR does not occur when the associated interrupt
acknowledge signal asserts and INTC_SSCIR0_3–INTC_SSCIR4_7 is written at a time such that the PRI
value in the associated INTC_CPR register would need to be pushed and the previously last pushed PRI
value would need to be popped simultaneously. In this case, PRI in the associated INTC_CPR is updated
with the new priority, and the associated LIFO is neither pushed or popped.
16.4.1.3 Debug mode
The INTC operation in debug mode is identical to its operation in normal mode.
16.4.1.4 Stop mode
The INTC supports STOP mode. The INTC can have its clock input disabled at any time by the clock
driver on the device. While its clocks are disabled, the INTC registers are not accessible.
The INTC requires clocking in order for a peripheral interrupt request to generate an interrupt request to
the processor. Since the INTC is not clocked in STOP mode, peripheral interrupt requests can not be used
as a wakeup source, unless the device supports that interrupt request as a wakeup source.
16.5 Memory map and register description
16.5.1 Module memory map
Table 16-2 shows the INTC memory map.
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