Freescale Semiconductor MPC5604B - Core Registers and Programmers Model

MPC5604B/C Microcontroller Reference Manual, Rev. 8
266 Freescale Semiconductor
• Watchpoint Trigger enable of Program Trace Messaging
• Auxiliary interface for higher data input/output
— Configurable (min/max) Message Data Out pins (nex_mdo[n:0])
— One (1) or two (2) Message Start/End Out pins (nex_mseo_b[1:0])
— One (1) Read/Write Ready pin (nex_rdy_b) pin
— One (1) Watchpoint Event pin (nex_evto_b)
— One (1) Event In pin (nex_evti_b)
— One (1) MCKO (Message Clock Out) pin
• Registers for Program Trace, Ownership Trace and Watchpoint Trigger control
• All features controllable and configurable via the JTAG port
15.5 Core registers and programmer’s model
This section describes the registers implemented in the e200z0h cores. It includes an overview of registers
defined by the Power Architecture platform, highlighting differences in how these registers are
implemented in the e200 core, and provides a detailed description of e200-specific registers. Full
descriptions of the architecture-defined register set are provided in the Power Architecture specification.
The Power Architecture defines register-to-register operations for all computational instructions. Source
data for these instructions are accessed from the on-chip registers or are provided as immediate values
embedded in the opcode. The three-register instruction format allows specification of a target register
distinct from the two source registers, thus preserving the original data for use by other instructions. Data
is transferred between memory and registers with explicit load and store instructions only.
Figure 15-2, and Figure 15-1 show the e200 register set including the registers which are accessible while
in supervisor mode, and the registers which are accessible in user mode. The number to the right of the
special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register
(for example, the integer exception register (XER) is SPR 1).
NOTE
e200z0h is a 32-bit implementation of the Power Architecture specification.
In this document, register bits are sometimes numbered from bit 0 (Most
Significant Bit) to 31 (Least Significant Bit), rather than the Book E
numbering scheme of 32:63, thus register bit numbers for some registers in
Book E are 32 higher.
Where appropriate, the Book E defined bit numbers are shown in
parentheses.