MPC5604B/C Microcontroller Reference Manual, Rev. 8
456 Freescale Semiconductor
of this MB is EMPTY, so the message is stored there. When the second message arrives, the matching
algorithm will find MB number 2 again, but it is not “free to receive”, so it will keep looking and find MB
number 5 and store the message there. If yet another message with the same ID arrives, the matching
algorithm finds out that there are no matching MBs that are “free to receive”, so it decides to overwrite the
last matched MB, which is number 5. In doing so, it sets the Code field of the MB to indicate OVERRUN.
The ability to match the same ID in more than one MB can be exploited to implement a reception queue
(in addition to the full featured FIFO) to allow more time for the CPU to service the MBs. By programming
more than one MB with the same ID, received messages will be queued into the MBs. The CPU can
examine the Time Stamp field of the MBs to determine the order in which the messages arrived.
The matching algorithm described above can be changed to be the same one used in previous versions of
the FlexCAN module. When the BCC bit in MCR is negated, the matching algorithm stops at the first MB
with a matching ID that it founds, whether this MB is free or not. As a result, the message queueing feature
does not work if the BCC bit is negated.
Matching to a range of IDs is possible by using ID Acceptance Masks. FlexCAN supports individual
masking per MB. Please refer to Section 22.3.4.13, “Rx Individual Mask Registers
(RXIMR0–RXIMR63). During the matching algorithm, if a mask bit is asserted, then the corresponding
ID bit is compared. If the mask bit is negated, the corresponding ID bit is “don’t care”. Please note that the
Individual Mask Registers are implemented in SRAM, so they are not initialized out of reset. Also, they
can only be programmed if the BCC bit is asserted and while the module is in Freeze Mode.
FlexCAN also supports an alternate masking scheme with only three mask registers (RGXMASK,
RX14MASK and RX15MASK) for backwards compatibility. This alternate masking scheme is enabled
when the BCC bit in the MCR is negated.
22.4.7 Data coherence
In order to maintain data coherency and FlexCAN proper operation, the CPU must obey the rules described
in Transmit process and Section 22.4.5, “Receive process. Any form of CPU accessing an MB structure
within FlexCAN other than those specified may cause FlexCAN to behave in an unpredictable way.
22.4.7.1 Transmission abort mechanism
The abort mechanism provides a safe way to request the abortion of a pending transmission. A feedback
mechanism is provided to inform the CPU if the transmission was aborted or if the frame could not be
aborted and was transmitted instead. In order to maintain backwards compatibility, the abort mechanism
must be explicitly enabled by asserting the AEN bit in the MCR.
In order to abort a transmission, the CPU must write a specific abort code (1001) to the Code field of the
Control and Status word. When the abort mechanism is enabled, the active MBs configured as trasmission
must be aborted first and then they may be updated. If the abort code is written to an MB that is currently
being transmitted, or to an MB that was already loaded into the SMB for transmission, the write operation
is blocked and the MB is not deactivated, but the abort request is captured and kept pending until one of
the following conditions are satisfied:
• The module loses the bus arbitration
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