Freescale Semiconductor MPC5604B - Page 461

MPC5604B/C Microcontroller Reference Manual, Rev. 8
450 Freescale Semiconductor
22.3.4.13 Rx Individual Mask Registers (RXIMR0–RXIMR63)
These registers are used as acceptance masks for ID filtering in Rx MBs and the FIFO. If the FIFO is not
enabled, one mask register is provided for each available Message Buffer, providing ID masking capability
on a per Message Buffer basis. When the FIFO is enabled (FEN bit in MCR is set), the first 8 Mask
Offset: 0x0030 Access: Read/write
0123456789101112131415
R
BUF 31I BUF 30I BUF 29I BUF 28I BUF 27I BUF 26I BUF 25I BUF 24I BUF 23I BUF 22I BUF 21I BUF 20I BUF 19I BUF 18I BUF 17I BUF 16I
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BUF 15I BUF 14I BUF 13I BUF 12I BUF 11I BUF 10I
BUF 9I BUF 8I BUF 7I BUF 6I BUF 5I BUF 4I BUF 3I BUF 2I BUF 1I BUF 0I
W
Reset0000000000000000
Figure 22-14. Interrupt Flags 1 Register (IFLAG1)
Table 22-17. IFLAG1 field descriptions
Field Description
BUF31I –
BUF8I
Buffer MB
i
Interrupt
Each bit flags the respective FlexCAN Message Buffer (MB8 to MB31) interrupt.
1 = The corresponding MB has successfully completed transmission or reception
0 = No such occurrence
BUF7I Buffer MB7 Interrupt or “FIFO Overflow”
If the FIFO is not enabled, this bit flags the interrupt for MB7. If the FIFO is enabled, this flag
indicates an overflow condition in the FIFO (frame lost because FIFO is full).
1 = MB7 completed transmission/reception or FIFO overflow
0 = No such occurrence
BUF6I Buffer MB6 Interrupt or “FIFO Warning”
If the FIFO is not enabled, this bit flags the interrupt for MB6. If the FIFO is enabled, this flag
indicates that 5 out of 6 buffers of the FIFO are already occupied (FIFO almost full).
1 = MB6 completed transmission/reception or FIFO almost full
0 = No such occurrence
BUF5I Buffer MB5 Interrupt or “Frames available in FIFO”
If the FIFO is not enabled, this bit flags the interrupt for MB5. If the FIFO is enabled, this flag
indicates that at least one frame is available to be read from the FIFO.
1 = MB5 completed transmission/reception or frames available in the FIFO
0 = No such occurrence
BUF4I – BUF0I Buffer MB
i
Interrupt or “reserved”
If the FIFO is not enabled, these bits flag the interrupts for MB0 to MB4. If the FIFO is enabled, these
flags are not used and must be considered as reserved locations.
1 = Corresponding MB completed transmission/reception
0 = No such occurrence