MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 763
Chapter 31
Error Correction Status Module (ECSM)
31.1 Introduction
The Error Correction Status Module (ECSM) provides a myriad of miscellaneous control functions for the
device including program-visible information about configuration and revision levels, a reset status
register, and information on memory errors reported by error-correcting codes.
31.2 Overview
The Error Correction Status Module is mapped into the IPS space and supports a number of miscellaneous
control functions for the device.
31.3 Features
The ECSM includes these features:
• Program-visible information on the device configuration and revision
• Registers for capturing information on memory errors due to error-correction codes
• Registers to specify the generation of single- and double-bit memory data inversions for test
purposes to check ECC protection
• Configuration for additional SRAM WS for system frequency above 64 + 4% MHz
31.4 Memory map and register description
This section details the programming model for the Error Correction Status Module. This is a 128-byte
space mapped to the region serviced by an IPS bus controller.
31.4.1 Memory map
The Error Correction Status Module does not include any logic which provides access control. Rather, this
function is supported using the standard access control logic provided by the IPS controller.
Table 31-1 shows the ECSM’s memory map.
Table 31-1. ECSM memory map
Base address: 0xFFF4_0000
Address offset Register Location
0x00 Processor Core Type Register (PCT) on page 765
0x02 SoC-Defined Platform Revision Register (REV) on page 765
0x04 Reserved
0x08 IPS On-Platform Module Configuration Register (IOPMC) on page 765
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