Freescale Semiconductor MPC5604B - Platform Flash Memory Controller

MPC5604B/C Microcontroller Reference Manual, Rev. 8
714 Freescale Semiconductor
On delivery the TestFlash nonvolatile image is at all ‘1’s, meaning all sectors are locked.
By programming the nonvolatile locations in TestFlash the selected sectors can be unlocked.
Being the TestFlash One Time Programmable (that is, not erasable), once unlocked the sectors cannot be
locked again.
Of course, on the contrary, all the volatile registers can be written at 0 or 1 at any time, therefore the user
application can lock and unlock sectors when desired.
27.6.3.5.2 Censored mode
The Censored Mode information is stored in nonvolatile flash memory cells located in the Shadow Sector.
This information is read once during the flash memory initialization phase following the exiting from
Reset and is stored in volatile registers that act as actuators.
The reset state of all the Volatile Censored Mode Registers is the protected state.
All the nonvolatile Censored Mode registers can be programmed through a normal Double Word Program
operation at the related locations in the Shadow Sector.
The nonvolatile Censored Mode registers can be erased by erasing the Shadow Sector.
• The nonvolatile Censored Mode Registers are physically located in the Shadow Sector their bits
can be programmed to ‘0’ and restored to ‘1’ by erasing the Shadow Sector.
• The Volatile Censored Mode Registers are registers not accessible by the user application.
The flash memory module provides two levels of protection against piracy:
• If bits CW15:0 of NVSCC0 are programmed at 0x55AA and NVSC1 = NVSCC0 the Censored
Mode is disabled, while all the other possible values enable the Censored Mode.
• If bits SC15:0 of NVSCC0 are programmed at 0x55AA and NVSC1 = NVSCC0 the Public Access
is disabled, while all the other possible values enable the Public Access.
The parts are delivered to the user with Censored Mode and Public Access disabled.
27.7 Platform flash memory controller
27.7.1 Introduction
The platform flash memory controller acts as the interface between the system bus (AHB-Lite 2.v6) and
up to two banks of integrated flash memory arrays (Program and Data). It intelligently converts the
protocols between the system bus and the dedicated flash memory array interfaces.
A block diagram of the e200z0h Power Architecture reduced product platform (RPP) reference design is
shown below in Figure 27-38 with the platform flash memory controller module and its attached
off-platform flash memory arrays highlighted.