MPC5604B/C Microcontroller Reference Manual, Rev. 8
172 Freescale Semiconductor
This mode is intended as an extreme low-power mode with
• the core, the flashes, and almost all peripherals and memories powered down
and to be used by software
• to wait until it is required to do something with no need to react quickly (i.e. allow for system
power-up and system clock source to be re-started)
The exit sequence of this mode is similar to the reset sequence. However, in addition to booting from the
default location, the device can also be configured to boot from the backup SRAM (see the RGM_STDBY
register description in the MC_RGM chapter for details). In the case of booting from backup SRAM, it is
also possible to keep the flashes disabled by writing “01” to the CFLAON and DFLAON fileds in the
ME_DRUN_MC register prior to STANDBY entry.
If there is a STANDBY mode request while any wakeup event is active, the device mode does not change.
All power domains except power domain #0 are configurable in this mode in order to reduce leakage
consumption. Active power domains are determined by the power configuration register PCU_PCONF2
of the MC_PCU.
8.4.3 Mode Transition Process
The process of mode transition follows the following steps in a pre-defined manner depending on the
current device mode and the requested target mode. In many cases of mode transition, not all steps need
to be executed based on the mode control information, and some steps may not be valid according to the
mode definition itself.
8.4.3.1 Target Mode Request
The target mode is requested by accessing the ME_MCTL register with the required keys. This mode
transition request by software must be a valid request satisfying a set of pre-defined rules to initiate the
process. If the request fails to satisfy these rules, it is ignored, and the TARGET_MODE bit field is not
updated. An optional interrupt can be generated for invalid mode requests. Refer to Section 8.4.5, “Mode
Transition Interrupts for details.
In the case of mode transitions occurring because of hardware events such as a reset, a SAFE mode request,
or interrupt requests and wakeup events to exit from low-power modes, the TARGET_MODE bit field of
the ME_MCTL register is automatically updated with the appropriate target mode. The mode change
process start is indicated by the setting of the mode transition status bit S_MTRANS of the ME_GS
register.
A RESET mode requested via the ME_MCTL register is passed to the MC_RGM, which generates a
global system reset and initiates the reset sequence. The RESET mode request has the highest priority, and
the MC_ME is kept in the RESET mode during the entire reset sequence.
The SAFE mode request has the next highest priority after reset which can be generated by software via
the ME_MCTL register from all software running modes including DRUN, RUN0…3, and TEST or by
the MC_RGM after the detection of system hardware failures, which may occur in any mode.
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