MPC5604B/C Microcontroller Reference Manual, Rev. 8
256 Freescale Semiconductor
14.4 Functional description
As the CAN sampler is driven by the 16 MHz fast internal RC oscillator (or “FIRC”) to properly sample
the CAN identifier, two modes are possible depending on both the CAN baud rate and low power mode
used:
• Immediate sampling on falling edge detection (first CAN frame): This mode is used when the
FIRC is available in LP mode (for example, STOP or HALT).
• Sampling on next frame (second CAN frame): This mode is used when the FIRC is switched off
in LP mode (for example, STANDBY). Due to the start-up times of both the voltage regulator and
the FIRC (~10 µs), the CAN sampler would miss the first bits of a CAN identifier sent at 500 kbps.
Therefore, the first identifier is ignored and the sampling is performed on the first falling edge of
after interframe space.
The CAN sampler is in power domain 0 and maintains register settings throughout low power modes. The
CAN sampler performs sampling on a user-selected CAN Rx port among six Rx ports available, normally
when the device is in STANDBY or STOP mode, storing the samples in internal registers. The user is
required to configure the baud rate to achieve eight samples per CAN nominal bit. It does not perform any
sort of filtering on input samples. Thereafter the software must enable the sampler by setting the
CAN_SMPLR_EN bit in the CR register. It then becomes the master controller for accessing the internal
registers implemented for storing samples.
The CAN sampler, when enabled, waits for a low pulse on the selected Rx line, taking it as a valid bit of
the first CAN frame and generates the RC wakeup request which can be used to start the FIRC. Depending
upon the mode, it stores the first 8 samples of the 48 bits on selected Rx line or skips the first frame and
stores 8 bits for first 48 bits of second frame. In FF_MODE, it samples the CAN Rx line on the FIRC clock
and stores the 8 samples of first 48 bits (384 samples). In SF_MODE, it samples the Rx and waits for 11
consecutive dominant bits ( 11 * 8 samples), taking it as the end of first frame. It then waits for first low
pulse on the Rx, taking it as a valid Start of Frame (SOF) of the second frame. The sampler takes 384
samples (48 bytes * 8) using the FIRC clock (configuring 8 samples per nominal bit) of the second frame,
including the SOF bit. These samples are stored in consecutive addresses of the (12 x 32) internal registers.
The RX_COMPLETE bit is set to ‘1’, indicating that sampling is complete.
Software should now process the sampled data by first becoming master for accessing samples internal
registers by resetting the CAN_SMPLR_EN bit. The sampler will need to be enabled again to start waiting
for a new sampling routine.
14.4.1 Enabling/Disabling the CAN sampler
The CAN sampler is disabled on reset and the CPU is able to access the 12 registers used for storing
samples. The CAN sampler must be enabled before going into STANDBY or STOP mode by setting the
CAN_SMPLR_EN bit in the Control Register (CR) by writing ‘1’ to this bit.
In case of any activity on the selected Rx line, the sampler enables the 16 MHz fast internal RC oscillator.
When bit CAN_SMPLR_EN is reset to 0, the sampler should receive at last three FIRC clock pulses to
reset itself, after which the FIRC can be switched off.
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