MPC5604B/C Microcontroller Reference Manual, Rev. 8
98 Freescale Semiconductor
After system reset, the oscillator is put to powerdown state and software has to switch on when required.
Whenever the SXOSC is switched on from off state, the OSCCNT counter starts and when it reaches the
value EOCV[7:0]×512, the oscillator clock is made available to the system.
The oscillator circuit can be bypassed by writing SXOSC_CTL[OSCBYP] bit to ‘1’. This bit can only be
set by software. A system reset is needed to reset this bit. In this bypass mode, the output clock has the
same polarity as the external clock applied on the OSC32K_EXTAL pin and the oscillator status is forced
to ‘1’. The bypass configuration is independent of the powerdown mode of the oscillator.
Table 6-4 shows the truth table of different configurations of the oscillator.
The SXOSC clock can be further divided by a configurable factor in the range 1 to 32 to generate the
divided clock to match system requirements. This division factor is specified by SXOSC_CTL[OSCDIV]
field.
6.4.4 Register description
Table 6-4. SXOSC truth table
SXOSC_CTL fields
OSC32K_XTAL OSC32K_EXTAL SXOSC Oscillator MODE
OSCON OSCBYP
0 0 No crystal, High Z No crystal, High Z 0 Powerdown, IDDQ
x 1 x External clock OSC32K_EXTAL Bypass, OSC disabled
1 0 Crystal Crystal OSC32K_EXTAL Normal, OSC enabled
Ground External clock OSC32K_EXTAL Normal, OSC enabled
Address: 0xC3FE_0040 Access: Special read/write
0123456789101112131415
R
OSCBYP
1
1
You can read this field, and you can write a value of “1” to it. Writing a “0” has no effect. A reset will also clear this bit.
0000000
EOCV
W
RESET:
0000000010000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
000
OSCDIV
000000
S_OSC
OSCON
W
RESET:
0000000000000000
Figure 6-3. Slow External Crystal Oscillator Control Register (SXOSC_CTL)
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