Freescale Semiconductor MPC5604B - External Decode Signals Delay

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 603
The CEOCFR[0..2] contains the interrupt pending request status. If the user wants to clear a particular
interrupt event status, then writing a ‘1’ to the corresponding status bit clears the pending interrupt flag (at
this write operation all the other bits of the CEOCFR[0..2] must be maintained at ‘0’).
25.3.8 External decode signals delay
The ADC provides several external decode signals to select which external channel has to be converted.
In order to take into account the control switching time of the external analog multiplexer, a Decode
Signals Delay register (DSDR) is provided. The delay between the decoding signal selection and the actual
start of conversion can be programmed by writing the field DSD[0:7].
After having selected the channel to be converted, the MA[0:2] control lines are automatically reset. For
instance, in the event of normal scan conversion on ANP[0] followed by ANX[0,7] (ADC ch 71) all the
MA[0:2] bits are set and subsequently reset.
25.3.9 Power-down mode
The analog part of the ADC can be put in low power mode by setting the MCR[PWDN]. After releasing
the reset signal the ADC analog module is kept in power-down mode by default, so this state must be exited
before starting any operation by resetting the appropriate bit in the MCR.
The power-down mode can be requested at any time by setting the MCR[PWDN]. If a conversion is
ongoing, the ADC must complete the conversion before entering the power down mode. In fact, the ADC
enters power-down mode only after completing the ongoing conversion. Otherwise, the ongoing operation
should be aborted manually by resetting the NSTART bit and using the ABORTCHAIN bit.
MSR[ADCSTATUS] bit is set only when ADC enters power-down mode.
After the power-down phase is completed the process ongoing before the power-down phase must be
restarted manually by setting the appropriate MCR[START] bit.
Resetting MCR[PWDN] bit and setting MCR[NSTART] or MCR[JSTART] bit during the same cycle is
forbidden.
If a CTU trigger pulse is received during power-down, it is discarded.
If the CTU is enabled and the CSR[CTUSTART] bit is ‘1’, then the MCR[PWDN] bit cannot be set.
When CTU trigger mode is enabled, the application has to wait for the end of conversion (CTUSTART bit
automatically reset).
25.3.10 Auto-clock-off mode
To reduce power consumption during the IDLE mode of operation (without going into power-down mode),
an “auto-clock-off” feature can be enabled by setting the MCR[ACKO] bit. When enabled, the analog
clock is automatically switched off when no operation is ongoing, that is, no conversion is programmed
by the user.