Freescale Semiconductor MPC5604B - Functional Description

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 761
30.6 Functional description
The SWT is a 32-bit timer designed to enable the system to recover in situations such as software getting
trapped in a loop or if a bus transaction fails to terminate. It includes a a control register (SWT_CR), an
interrupt register (SWT_IR), time-out register (SWT_TO), a window register (SWT_WN), a service
register (SWT_SR) and a counter output register (SWT_CO).
The SWT_CR includes bits to enable the timer, set configuration options and lock configuration of the
module. The watchdog is enabled by setting the SWT_CR.WEN bit. The reset value of the
SWT_CR.WEN bit is device specific1 (enabled). This last bit is cleared when exiting ME RESET mode
in case flash user option bit 31 (WATCHDOG_EN) is ‘0’. If the reset value of this bit is 1, the watchdog
starts operation automatically after reset is released. Some devices can be configured to clear this bit
automatically during the boot process.
The SWT_TO register holds the watchdog time-out period in clock cycles unless the value is less than
0x100 in which case the time-out period is set to 0x100. This time-out period is loaded into an internal
32-bit down counter when the SWT is enabled and each time a valid service sequence is written. The
SWT_CR.CSL bit selects which clock (system or oscillator) is used to drive the down counter. The reset
value of the SWT_TO register is device-specific as described previously.
The configuration of the SWT can be locked through use of either a soft lock or a hard lock. In either case,
when locked the SWT_CR, SWT_TO and SWT_WN registers are read only. The hard lock is enabled by
setting the SWT_CR.HLK bit which can only be cleared by a reset. The soft lock is enabled by setting the
SWT_CR.SLK bit and is cleared by writing the unlock sequence to the service register. The unlock
sequence is a write of 0xC520 followed by a write of 0xD928 to the SWT_SR.WSC field. There is no
timing requirement between the two writes. The unlock sequence logic ignores service sequence writes
and recognizes the 0xC520, 0xD928 sequence regardless of previous writes. The unlock sequence can be
written at any time and does not require the SWT_CR.WEN bit to be set.
When enabled, the SWT requires periodic execution of the watchdog servicing sequence. The service
sequence is a write of 0xA602 followed by a write of 0xB480 to the SWT_SR.WSC field. Writing the
service sequence loads the internal down counter with the time-out period. There is no timing requirement
between the two writes. The service sequence logic ignores unlock sequence writes and recognizes the
0xA602, 0xB480 sequence regardless of previous writes. Accesses to SWT registers occur with no
peripheral bus wait states. (The peripheral bus bridge may add one or more system wait states.) However,
due to synchronization logic in the SWT design, recognition of the service sequence or configuration
changes may require up to three system plus seven counter clock cycles.
Table 30-7. SWT_CO field descriptions
Field Description
CNT Watchdog Count. When the watchdog is disabled (SWT_CR.WENSWT_CR.=0) this field shows the
value of the internal down counter. When the watchdog is enabled the value of this field is
0x0000_0000. Values in this field can lag behind the internal counter value for up to six system plus
eight counter clock cycles. Therefore, the value read from this field immediately after disabling the
watchdog may be higher than the actual value of the internal counter.